High resolution Low Latency Sigma Delta ADC

General description:

The core of the low latency ADC consist of a high-resolution sigma-delta modulator. The latency is only one clock cycle, which makes the converter ideally suited for application in control loops. This low latency is made possible by a bitstream output that is fed back into a DAC, which creates a tracking ADC behavior where the output accurately tracks the input signal inside the signal bandwidth. The DAC principle also makes the system robust towards jitter and other error sources typically associated with 1-bit converters.

The low latency ADC can convert both single-ended and differential signals with high accuracy and it can convert signals with amplitudes and biasing levels well outside its own supply level, with the input resistors acting as level shifters and V-I converters. The converter has two low-latency bitstream outputs; q_dm for differential mode and q_cm for common mode representation of the input signal.

More information, including the datasheet, is available under NDA.

Block diagram:

Features:

• Dynamic range: 120dB (20Hz – 20kHz) 
• Full-scale input bandwidth: 100kHz 
• Power < 20mW 
• Low offset 
• High jitter tolerance 
• Differential or single-ended input
• Two low-latency bitstream outputs
  
• Wide input range (outside supply and true-ground)
• Current input possible (without Rin)
• Continuous time loopfilter for alias suppression
• Design is scalable with regard to area, power and performance

Applications:

• High-quality audio (codec, digital amplifier)

• High-precision control systems, such as active noise reduction

• Automatic test equipment

• Instrumentation