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2008

A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator
Gierkink, S.L.J. IEEE Journal of Solid-State Circuits, Vol. 43, No. 8, Aug. 2008, pp. 1763-1771.

A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL
S.L.J. Gierkink Proceedings of the 2008 CICC, Sept. 2008.

Wideband CMOS Receivers exploiting Simultaneous Output Balancing and NoiseDistortion Canceling
Blaakmeer, S.C., Klumperink, E.A.M., Leenaerts, D.M.W., Nauta, B. Invited paper for the focussed session on "Linear Receiver Techniques" of the European Microwave Integrated Circuit Conference (EuMIC), October 27-29, pg. 163-166, Amsterdam 2008.

Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling
Blaakmeer, S.C., Klumperink, E.A.M., Leenaerts, D.M.W., Nauta, B., IEEE Journal of Solid-State Circuits, vol.43, no.6, pp.1341-1350, June 2008